From 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 21 Sep 2022 15:46:43 +0200
Subject: Test fixes for latest iverilog

---
 techlibs/achronix/speedster22i/cells_sim.v |  3 +--
 techlibs/sf2/cells_sim.v                   |  2 +-
 tests/simple/memory.v                      | 14 ++++++++++++--
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index 6c87adb94..fc15e0966 100644
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -68,9 +68,8 @@ end
 assign dout = combout_rt & 1'b1;
 endmodule
 
-module DFF (output q,
+module DFF (output reg q,
             input  d, ck);
-   reg             q;
    always @(posedge ck)
      q <= d;
 
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index 02335404b..b5438e44c 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -162,7 +162,7 @@ module ARI1 (
 	wire F1 = INIT[8 + Fsel];
 	wire Yout = A ? F1 : F0;
 	assign Y = Yout;
-	wire S = FCI ^ Yout;
+	assign S = FCI ^ Yout;
 	wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
 	wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
 	assign FCO = P ? FCI : G;
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index f38bdafd3..b478d9409 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -137,8 +137,13 @@ endmodule
 
 // ----------------------------------------------------------
 
-module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_sync(clk, rst, idx, din, dout);
+    input clk;
+    input rst;
     (* gentb_constant=0 *) wire rst;
+    input [2:0] idx;
+    input [7:0] din;
+    output [7:0] dout;
     reg [7:0] test [0:7];
     integer i;
     always @(posedge clk) begin
@@ -156,8 +161,13 @@ module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, ou
     assign dout = test[idx];
 endmodule
 
-module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_async(clk, rst, idx, din, dout);
+    input clk;
+    input rst;
     (* gentb_constant=0 *) wire rst;
+    input [2:0] idx;
+    input [7:0] din;
+    output [7:0] dout;
     reg [7:0] test [0:7];
     integer i;
     always @(posedge clk or posedge rst) begin
-- 
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