From 1af7d6121f697b60e6eaabcabd50c49c90d09402 Mon Sep 17 00:00:00 2001
From: Dag Lem <dag@nimrod.no>
Date: Wed, 8 Mar 2023 20:25:39 +0100
Subject: Added test for dynamic indexing within struct members

---
 tests/svtypes/struct_dynamic_range.sv | 67 +++++++++++++++++++++++++++++++++++
 tests/svtypes/struct_dynamic_range.ys |  4 +++
 2 files changed, 71 insertions(+)
 create mode 100644 tests/svtypes/struct_dynamic_range.sv
 create mode 100644 tests/svtypes/struct_dynamic_range.ys

diff --git a/tests/svtypes/struct_dynamic_range.sv b/tests/svtypes/struct_dynamic_range.sv
new file mode 100644
index 000000000..ce1f14670
--- /dev/null
+++ b/tests/svtypes/struct_dynamic_range.sv
@@ -0,0 +1,67 @@
+module range_shift_mask(
+    input logic [2:0] addr_i,
+    input logic [7:0] data_i,
+    input logic [2:0] addr_o,
+    output logic [7:0] data_o
+);
+    // (* nowrshmsk = 0 *)
+    struct packed {
+        logic [7:0] msb;
+        logic [0:3][7:0] data;
+        logic [7:0] lsb;
+    } s;
+
+    always_comb begin
+        s = '1;
+        s.data[addr_i] = data_i;
+        data_o = s.data[addr_o];
+    end
+endmodule
+
+module range_case(
+    input logic [2:0] addr_i,
+    input logic [7:0] data_i,
+    input logic [2:0] addr_o,
+    output logic [7:0] data_o
+);
+    // (* nowrshmsk = 1 *)
+    struct packed {
+        logic [7:0] msb;
+        logic [0:3][7:0] data;
+        logic [7:0] lsb;
+    } s;
+
+    always_comb begin
+        s = '1;
+        s.data[addr_i] = data_i;
+        data_o = s.data[addr_o];
+    end
+endmodule
+
+module top;
+    logic [7:0] data_shift_mask1;
+    range_shift_mask range_shift_mask1(3'd1, 8'h7e, 3'd1, data_shift_mask1);
+    logic [7:0] data_shift_mask2;
+    range_shift_mask range_shift_mask2(3'd1, 8'h7e, 3'd2, data_shift_mask2);
+    logic [7:0] data_shift_mask3;
+    range_shift_mask range_shift_mask3(3'd1, 8'h7e, 3'd4, data_shift_mask3);
+
+    always_comb begin
+        assert(data_shift_mask1 === 8'h7e);
+        assert(data_shift_mask2 === 8'hff);
+        assert(data_shift_mask3 === 8'hxx);
+    end
+
+    logic [7:0] data_case1;
+    range_case range_case1(3'd1, 8'h7e, 3'd1, data_case1);
+    logic [7:0] data_case2;
+    range_case range_case2(3'd1, 8'h7e, 3'd2, data_case2);
+    logic [7:0] data_case3;
+    range_case range_case3(3'd1, 8'h7e, 3'd4, data_case3);
+
+    always_comb begin
+        assert(data_case1 === 8'h7e);
+        assert(data_case2 === 8'hff);
+        assert(data_case3 === 8'hxx);
+    end
+endmodule
diff --git a/tests/svtypes/struct_dynamic_range.ys b/tests/svtypes/struct_dynamic_range.ys
new file mode 100644
index 000000000..d09e1924d
--- /dev/null
+++ b/tests/svtypes/struct_dynamic_range.ys
@@ -0,0 +1,4 @@
+read_verilog -sv struct_dynamic_range.sv
+prep -top top
+flatten
+sat -enable_undef -verify -prove-asserts
-- 
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