| Commit message (Collapse) | Author | Age | Files | Lines |
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verilog: Fix const eval of unbased unsized constants
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When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.
This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.
The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
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* ABC9: RAMB36E1 Bug Patch
* Add simplified testcase
* Also fix xaiger writer for under-width output ports
* Remove old testcase
* Missing top-level input port
* Fix tabs
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
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The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
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This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
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Out of bounds checking for struct/union members
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This guards against access to bits outside of struct/union
members via dynamic indexing.
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Currently, only constant indices are checked.
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muxcover: do not add decode muxes with x inputs
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Signed-off-by: gatecat <gatecat@ds0.me>
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Made redundant by TDP test(s) in memories.ys
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Explicitly declare -top in synth_intel_alm.
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Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
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iCE40 SPRAM and Xilinx URAM
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New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
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Uses verilog code from User Guide 901 (2021.1)
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Support for data and array queries on struct/union item expressions
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For now, $bits, $left, $right, $low, $high, and $size are supported.
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Add test for typenames using constants shadowed later on
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This possible edge case came up while reviewing #3555. It is currently
handled correctly, but there is no clear test coverage.
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Handle range offsets in packed arrays within packed structs
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This brings the metadata for packed arrays in packed structs
in line with the metadata for unpacked arrays, and correctly
handles the case when both lsb and msb in an address range are
non-zero.
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chformal: Add -coverenable option
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equiv_make: Add -make_assert option
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This adds a -make_assert flag to equiv_make. When used, the pass generates
$eqx and $assert cells to encode equivalence instead of $equiv.
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tests: Fix path of yosys invocation in xprop tests
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Use `$finish(0)` to silently exit even when using recent iverlog
versions. Run `write_verilog -noexpr` before `write_verilog` as the
latter can modify the design.
This also enables checking the tests results, as xprop should be in a
state where the existing tests pass.
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For now xprop test failures are still expected and ignored, but without
this change, they did not even run unless the yosys build was in path.
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* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
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backends/rtlil: Do not shorten a value with z bits to 'x
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