iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	verilog: fix sizing of ports with int types in module headers	Zachary Snow	2021-03-01	1	-0/+50
	Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.