| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | verilog: impose limit on maximum expression width | Zachary Snow | 2021-03-04 | 1 | -0/+16 |
| Designs with unreasonably wide expressions would previously get stuck allocating memory forever. | |||||
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index : iCE40/yosys | |
| [no description] |
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