| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -4/+38 |
| | | | | | No longer false warnings for memories and assertions | ||||
| * | reg_wire_error test needs the -sv flag so it is run via a script so it had ↵ | Udi Finkelstein | 2018-06-05 | 1 | -0/+40 |
| to be moved out of the tests/simple dir that only runs Verilog files | |||||
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index : iCE40/yosys | |
| [no description] |
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