| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | genrtlil: fix signed port connection codegen failures | Zachary Snow | 2021-02-05 | 1 | -4/+18 |
| | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used. | ||||
| * | genrtlil: fix mux2rtlil generated wire signedness | Zachary Snow | 2020-12-22 | 1 | -4/+9 |
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| * | Sign extend port connections where necessary | Zachary Snow | 2020-12-18 | 1 | -0/+76 |
| - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265 | |||||
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index : iCE40/yosys | |
| [no description] |
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