| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add missing .gitignore | Clifford Wolf | 2018-12-06 | 1 | -0/+8 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 7 | -2/+420 |
| | | | | | test case | ||||
| * | Basic test for checking correct synthesis of SystemVerilog interfaces | Ruben Undheim | 2018-10-18 | 5 | -0/+327 |
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index : iCE40/yosys | |
| [no description] |
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