index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
tests
/
svinterfaces
/
svinterface1.sv
Commit message (
Collapse
)
Author
Age
Files
Lines
*
Basic test for checking correct synthesis of SystemVerilog interfaces
Ruben Undheim
2018-10-18
1
-0
/
+117