| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | verific: Improve logic generated for SVA value change expressions | Jannis Harder | 2022-05-09 | 1 | -1/+3 |
| | | | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation | ||||
| * | Fix running sva tests | Miodrag Milanovic | 2022-05-09 | 1 | -4/+3 |
| | | |||||
| * | Add support for SVA sequence concatenation ranges via verific | Clifford Wolf | 2018-02-18 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Remove PSL example from tests/sva/ | Clifford Wolf | 2017-10-20 | 1 | -1/+1 |
| | | |||||
| * | Add simple VHDL+PSL example | Clifford Wolf | 2017-07-28 | 1 | -13/+24 |
| | | |||||
| * | Improve SVA tests, add Makefile and scripts | Clifford Wolf | 2017-07-27 | 1 | -0/+60 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |