iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09	1	-0/+18
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-0/+18
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09	1	-3/+43
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-0/+10
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+16
*	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13	1	-0/+19
*	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31	6	-0/+111
*	Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	2013-03-24	1	-1/+0
*	Added hansimem testcase (memory with async reset)	Clifford Wolf	2013-03-24	1	-0/+44
*	added ckeck for Icarus Verilog, otherwise the tests are silently stopped	Johann Glaser	2013-03-17	1	-0/+7
*	added more .gitignore files (make test)	Clifford Wolf	2013-01-05	1	-0/+2
*	initial import	Clifford Wolf	2013-01-05	19	-0/+905