iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	verilog: fix buf/not primitives with multiple outputs	Xiretza	2021-03-17	1	-0/+15
	From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.