| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | tests/simple: remove "nullglob" shopt | Xiretza | 2020-09-21 | 1 | -1/+0 |
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| * | Use `command -v` rather than `which` | Emily | 2019-09-03 | 1 | -1/+1 |
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| * | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 1 | -1/+2 |
| | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | ||||
| * | Add optional SEED=n command line option to Makefile, and -S n command line ↵ | Eric Smith | 2016-09-22 | 1 | -1/+12 |
| | | | | | option to test scripts, for deterministic regression tests. | ||||
| * | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 1 | -1/+1 |
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| * | Added note to "make test": use git checkout of iverilog | Clifford Wolf | 2014-07-16 | 1 | -1/+1 |
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| * | Added tests/realmath to "make test" | Clifford Wolf | 2014-06-15 | 1 | -1/+0 |
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| * | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 | 1 | -0/+7 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+3 |
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index : iCE40/yosys | |
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