| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix "make vgtest" so it runs to the end (but now it fails ;) | Claire Xenia Wolf | 2021-09-23 | 1 | -1/+1 |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
| * | verilog: fix case expression sign and width handling | Zachary Snow | 2021-05-25 | 1 | -0/+59 |
| - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements | |||||
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index : iCE40/yosys | |
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