| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | proc_prune: Make assign removal and promotion per-bit, remember promoted bits. | Marcelina Kościelnicka | 2021-08-14 | 1 | -0/+22 |
| | | | | | Fixes #2962. | ||||
| * | proc_rmdead: use explicit pattern set when there are no wildcards | Zachary Snow | 2021-07-29 | 2 | -0/+50 |
| | | | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen. | ||||
| * | proc_arst: Add special-casing of clock signal in conditionals. | Marcelina Kościelnicka | 2021-03-15 | 1 | -0/+31 |
| | | | | | | | | | | | | | | | | | | The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656. | ||||
| * | proc_dff: Fix emitted FF when a register is not assigned in async reset | Marcelina Kościelnicka | 2021-03-08 | 1 | -0/+23 |
| | | | | | Fixes #2619. | ||||
| * | proc_clean: fix order of switch insertion. | whitequark | 2019-08-19 | 4 | -0/+35 |
| Fixes #1268. | |||||
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index : iCE40/yosys | |
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