| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added autotest -e (do not use -noexpr on write_verilog) | Clifford Wolf | 2014-08-30 | 1 | -1/+1 |
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| * | Consolidated hana test benches into fewer files | Clifford Wolf | 2014-08-01 | 175 | -1332/+1622 |
| | | | | | | | | | for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc.. | ||||
| * | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 1 | -1/+1 |
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| * | Added note to "make test": use git checkout of iverilog | Clifford Wolf | 2014-07-16 | 1 | -1/+1 |
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| * | Added tests/realmath to "make test" | Clifford Wolf | 2014-06-15 | 1 | -1/+0 |
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| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 | 1 | -0/+2 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 159 | -0/+2734 |
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index : iCE40/yosys | |
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