| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 1 | -1/+0 |
| | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | ||||
| * | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 |
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| * | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 1 | -0/+24 |
| | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | ||||
| * | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add optional SEED=n command line option to Makefile, and -S n command line ↵ | Eric Smith | 2016-09-22 | 1 | -1/+13 |
| | | | | | option to test scripts, for deterministic regression tests. | ||||
| * | Some fixes in tests/asicworld/*_tb.v | Clifford Wolf | 2016-05-20 | 4 | -50/+41 |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -1/+1 |
| | | | | | Smaller this time | ||||
| * | Fixed CRLF line endings | Clifford Wolf | 2015-08-13 | 4 | -266/+266 |
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| * | Some ASCII encoding fixes (comments and docs) by Larry Doolittle | Clifford Wolf | 2015-08-13 | 1 | -1/+1 |
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| * | Some test related fixes | Clifford Wolf | 2015-02-12 | 3 | -150/+0 |
| | | | | | (incl. removal of three bad test cases) | ||||
| * | Added autotest -e (do not use -noexpr on write_verilog) | Clifford Wolf | 2014-08-30 | 1 | -1/+1 |
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| * | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 1 | -1/+1 |
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| * | Added note to "make test": use git checkout of iverilog | Clifford Wolf | 2014-07-16 | 1 | -1/+1 |
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| * | Added tests/realmath to "make test" | Clifford Wolf | 2014-06-15 | 1 | -1/+0 |
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| * | Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v | Clifford Wolf | 2013-05-24 | 1 | -1/+3 |
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| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 | 1 | -0/+2 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 89 | -0/+2899 |
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index : iCE40/yosys | |
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