| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | tests: xilinx macc test to have initval, shorten BMC depth for runtime | Eddie Hung | 2020-05-25 | 1 | -2/+2 |
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| * | Make test without iopads | Miodrag Milanovic | 2019-12-28 | 1 | -4/+4 |
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| * | Revert "Fix xilinx tests, when iopads are default" | Miodrag Milanovic | 2019-12-28 | 1 | -2/+2 |
| | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c. | ||||
| * | Fix xilinx tests, when iopads are default | Miodrag Milanovic | 2019-12-21 | 1 | -2/+2 |
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| * | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | ||||
| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 1 | -0/+31 |
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index : iCE40/yosys | |
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