iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24	1	-4/+4
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*	Fixed xilinx/example_sim_counter test bench	Clifford Wolf	2013-11-24	1	-1/+1
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*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23	1	-1/+1
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*	[EXAMPLES] Ported the mojo counter example to Zynq ZED board.	James Walmsley	2013-10-27	4	-0/+56
\| \| \| \|	Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
*	Cleanups in xilinx examples	Clifford Wolf	2013-10-27	3	-144/+28
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*	Added synth_xilinx command	Clifford Wolf	2013-10-27	2	-0/+219
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*	Moved simple xilinx counter sim example to subdir	Clifford Wolf	2013-10-27	3	-0/+0
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*	Xilinx mojo_counter example is now working	Clifford Wolf	2013-10-27	3	-4/+9
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*	Renamed techlibs/xilinx7 to techlibs/xilinx	Clifford Wolf	2013-10-26	8	-0/+316