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* atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
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* Fix $__XILINX_MUXF78 box timingEddie Hung2019-07-011-1/+1
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* Revert "Fix broken MUXFx box, use MUXF7x2 box instead"Eddie Hung2019-07-013-37/+36
| | | | This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90.
* Fix broken MUXFx box, use MUXF7x2 box insteadEddie Hung2019-07-013-36/+37
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* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-292-16/+8
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| * install *_nowide.lut filesEddie Hung2019-06-291-0/+2
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| * Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
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* | Restore $__XILINX_MUXF78 const optimisationEddie Hung2019-06-281-24/+24
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* | Clean up trimming leading 1'bx in A during techmappnigEddie Hung2019-06-281-15/+9
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* | Fix CARRY4 abc_box_idEddie Hung2019-06-281-1/+1
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-283-9/+4
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| * Reduce diff with upstreamEddie Hung2019-06-271-4/+2
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| * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-2/+2
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| * Remove redundant docEddie Hung2019-06-271-3/+0
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* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-271-7/+10
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| * Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
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| * Merge origin/masterEddie Hung2019-06-272-8/+9
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* | MUXF78 -> $__MUXF78 to indicate internalEddie Hung2019-06-261-1/+1
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* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-262-5/+6
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| * Update comment on boxesEddie Hung2019-06-261-2/+3
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| * Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
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* | synth_xilinx's muxcover call to be very conservative -- -nodecodeEddie Hung2019-06-261-1/+1
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* | Accidentally removed "simplemap $mux"Eddie Hung2019-06-261-0/+1
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* | Replace with <internal options>Eddie Hung2019-06-261-2/+2
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* | Rework help_mode for synth_xilinx -widemuxEddie Hung2019-06-261-22/+23
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* | Return to upstream synth_xilinx with opt -full and wreduceEddie Hung2019-06-261-19/+3
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* | Merge remote-tracking branch 'origin/eddie/fix1132' into xc7muxEddie Hung2019-06-261-1/+1
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| * | Simulation model verilog fixMiodrag Milanovic2019-06-261-1/+1
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* | | Instead of blocking wreduce on $mux, use -keepdc instead #1132Eddie Hung2019-06-261-2/+2
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* | | Do not call opt with -full before muxcoverEddie Hung2019-06-261-1/+1
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* | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-261-1/+1
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| * | Remove unused varEddie Hung2019-06-261-1/+1
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* | | Cleanup abc_box_idEddie Hung2019-06-262-10/+10
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* | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-262-11/+45
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| * | Add _nowide variants of LUT libraries in -nowidelut flowsEddie Hung2019-06-262-12/+28
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| * | Merge branch 'koriakin/xc7nocarrymux' into xaigEddie Hung2019-06-261-2/+20
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| | * \ Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into ↵Eddie Hung2019-06-261-4/+24
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| | | * synth_xilinx: Add -nocarry and -nomux options.Marcin Kościelnicki2019-04-301-7/+26
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| * | | Realistic delays for RAM32X1D tooEddie Hung2019-06-251-2/+2
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| * | | Add RAM32X1D box infoEddie Hung2019-06-252-4/+12
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| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-8/+72
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* | | | Rename -minmuxf to -widemuxEddie Hung2019-06-261-23/+23
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* | | | This optimisation doesn't seem to work...Eddie Hung2019-06-251-24/+24
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* | | | Realistic delays for RAM32X1D tooEddie Hung2019-06-241-2/+2
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-241-4/+4
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| * | | Use LUT delays for dist RAM delaysEddie Hung2019-06-241-4/+4
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* | | | Add RAM32X1D box infoEddie Hung2019-06-242-4/+12
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-242-0/+16
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| * | | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-242-0/+16
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* | | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7muxEddie Hung2019-06-245-8/+72
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