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iCE40/yosys
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xilinx
Commit message (
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Author
Age
Files
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Add unconditional match blocks for force RAM
Eddie Hung
2019-12-16
1
-4
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+36
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Update xc7/xcu bram rules
Eddie Hung
2019-12-16
1
-8
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+4
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Removing fixed attribute value to !ramstyle rules
Diego H
2019-12-15
1
-4
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+4
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Merging attribute rules into a single match block; Adding tests
Diego H
2019-12-15
1
-18
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+12
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Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
Diego H
2019-12-13
1
-0
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+19
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Merge pull request #1533 from dh73/bram_xilinx
Eddie Hung
2019-12-13
1
-6
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+9
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Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Diego H
2019-12-12
1
-5
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+5
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Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diego H
2019-12-12
1
-2
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+2
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Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diego H
2019-12-12
5
-633
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+868
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Adjusting Vivado's BRAM min bits threshold for RAMB18E1
Diego H
2019-11-27
1
-2
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+5
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abc9_map.v: fix Xilinx LUTRAM
Eddie Hung
2019-12-12
1
-6
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+6
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abc9_map.v: fix Xilinx LUTRAM
Eddie Hung
2019-12-12
1
-6
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+6
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Fix comment
Eddie Hung
2019-12-09
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-06
5
-633
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+868
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xilinx: Add tristate buffer mapping. (#1528)
Marcin Kościelnicki
2019-12-04
2
-9
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+16
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xilinx: Add models for LUTRAM cells. (#1537)
Marcin Kościelnicki
2019-12-04
3
-624
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+831
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xilinx: Add missing blackbox cell for BUFPLL.
Marcin Kościelnicki
2019-11-29
2
-0
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+21
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Remove creation of $abc9_control_wire
Eddie Hung
2019-12-06
1
-16
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+6
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abc9 to use mergeability class to differentiate sync/async
Eddie Hung
2019-12-06
1
-12
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+15
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Remove clkpart
Eddie Hung
2019-12-05
1
-4
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+0
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Revert "Special abc9_clock wire to contain only clock signal"
Eddie Hung
2019-12-05
1
-10
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+12
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Missing wire declaration
Eddie Hung
2019-12-04
1
-0
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+1
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abc9_map.v to transform INIT=1 to INIT=0
Eddie Hung
2019-12-04
1
-118
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+201
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Oh deary me
Eddie Hung
2019-12-04
1
-4
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+4
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output reg Q -> output Q to suppress warning
Eddie Hung
2019-12-04
1
-8
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+8
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abc9_map.v to do `zinit' and make INIT = 1'b0
Eddie Hung
2019-12-04
1
-70
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+112
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Add abc9_init wire, attach to abc9_flop cell
Eddie Hung
2019-12-03
1
-2
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+12
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Revert "Add INIT value to abc9_control"
Eddie Hung
2019-12-03
1
-8
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+8
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techmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung
2019-12-03
1
-6
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+5
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Add INIT value to abc9_control
Eddie Hung
2019-12-02
1
-8
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+8
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clkpart -unpart into 'finalize'
Eddie Hung
2019-11-28
1
-3
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+4
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ean call after abc{,9}
Eddie Hung
2019-11-27
1
-1
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+2
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Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung
2019-11-27
3
-25
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+30
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xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
3
-25
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+30
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Move 'clean' from map_luts to finalize
Eddie Hung
2019-11-26
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
2
-3
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+11
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-1
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+5
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xilinx: Use INV instead of LUT1 when applicable
Marcin Kościelnicki
2019-11-25
1
-2
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+6
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Special abc9_clock wire to contain only clock signal
Eddie Hung
2019-11-25
1
-12
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+10
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For abc9, run clkpart before ff_map and after abc9
Eddie Hung
2019-11-23
1
-0
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+2
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Merge branch 'eddie/xaig_dff_adff' into xaig_dff
Eddie Hung
2019-11-21
1
-12
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+16
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Do not drop async control signals in abc_map.v
Eddie Hung
2019-11-19
1
-12
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+16
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Add blackbox model for $__ABC9_FF_ so that clock partitioning works
Eddie Hung
2019-11-20
1
-0
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+3
*
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Fix INIT values
Eddie Hung
2019-11-20
1
-4
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+4
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-19
22
-23020
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+30968
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xilinx: Add simulation models for MULT18X18* and DSP48A*.
Marcin Kościelnicki
2019-11-19
3
-132
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+516
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synth_xilinx: Merge blackbox primitive libraries.
Marcin Kościelnicki
2019-11-06
11
-23234
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+29820
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xilinx: Add URAM288 mapping for xcup
David Shah
2019-10-23
5
-2
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+92
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xilinx: Add support for UltraScale[+] BRAM mapping
David Shah
2019-10-23
7
-416
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+1062
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xilinx: Support multiplier mapping for all families.
Marcin Kościelnicki
2019-10-22
9
-9
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+269
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