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* Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-076-155/+645
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| * Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-066-152/+642
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| | * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-065-1674/+509
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| | * | Fix spacingEddie Hung2020-01-021-1/+1
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| | * | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
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| | * | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-022-24/+44
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| | * | | Update commentsEddie Hung2020-01-021-11/+6
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| | * | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
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| | * | | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
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| | * | | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
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| | * | | Re-arrange FD orderEddie Hung2019-12-313-182/+182
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| | * | | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
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| | * | | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
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| | * | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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| | * | | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
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| | * | | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
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| | * | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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| | * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-308-21/+374
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| | * | | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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| | * | | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| | * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| | * | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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| | * | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
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| | * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1912-77/+967
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| | * | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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| | * | | | | | | Fix commentEddie Hung2019-12-091-1/+1
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| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-065-633/+868
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| | * | | | | | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
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| | * | | | | | | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
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| | * | | | | | | | Remove clkpartEddie Hung2019-12-051-4/+0
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| | * | | | | | | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.
| | * | | | | | | | Missing wire declarationEddie Hung2019-12-041-0/+1
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| | * | | | | | | | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-118/+201
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| | * | | | | | | | Oh deary meEddie Hung2019-12-041-4/+4
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| | * | | | | | | | output reg Q -> output Q to suppress warningEddie Hung2019-12-041-8/+8
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| | * | | | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0Eddie Hung2019-12-041-70/+112
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| | * | | | | | | | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
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| | * | | | | | | | Revert "Add INIT value to abc9_control"Eddie Hung2019-12-031-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22.
| | * | | | | | | | techmap abc_unmap.v before xilinx_srl -fixedEddie Hung2019-12-031-6/+5
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| | * | | | | | | | Add INIT value to abc9_controlEddie Hung2019-12-021-8/+8
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| | * | | | | | | | clkpart -unpart into 'finalize'Eddie Hung2019-11-281-3/+4
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| | * | | | | | | | ean call after abc{,9}Eddie Hung2019-11-271-1/+2
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| | * | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-273-25/+30
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| | * | | | | | | | | Move 'clean' from map_luts to finalizeEddie Hung2019-11-261-1/+1
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-252-3/+11
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| | * | | | | | | | | | Special abc9_clock wire to contain only clock signalEddie Hung2019-11-251-12/+10
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| | * | | | | | | | | | For abc9, run clkpart before ff_map and after abc9Eddie Hung2019-11-231-0/+2
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| | * | | | | | | | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-211-12/+16
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| | | * | | | | | | | | | Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
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