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* | Added missing ports and parameters to xilinx brams | Clifford Wolf | 2015-02-01 | 1 | -4/+18 | |
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* | Fixed xilinx FDSE sim model | Clifford Wolf | 2015-01-24 | 1 | -2/+2 | |
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* | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 7 | -9/+110 | |
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* | Refactoring of memory_bram and xilinx brams | Clifford Wolf | 2015-01-18 | 3 | -468/+55 | |
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* | Added synth_xilinx -retime -flatten | Clifford Wolf | 2015-01-17 | 1 | -2/+28 | |
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* | Added MUXCY and XORCY support to synth_xilinx | Clifford Wolf | 2015-01-17 | 4 | -2/+106 | |
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* | Added dff2dffe to synth_xilinx | Clifford Wolf | 2015-01-16 | 1 | -0/+2 | |
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* | Added more FF types to xilinx/cells.v | Clifford Wolf | 2015-01-16 | 1 | -25/+28 | |
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* | Fixed xilinx bram clock inverted config | Clifford Wolf | 2015-01-16 | 1 | -21/+35 | |
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* | Added FF cells to xilinx/cells_sim.v | Clifford Wolf | 2015-01-16 | 1 | -116/+116 | |
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* | Added Xilinx MUXF7 and MUXF8 support | Clifford Wolf | 2015-01-15 | 2 | -2/+30 | |
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* | Various cleanups in synth_xilinx command | Clifford Wolf | 2015-01-13 | 1 | -54/+8 | |
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* | Added add_share_file Makefile macro | Clifford Wolf | 2015-01-08 | 1 | -13/+4 | |
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* | added minimalistic xilinx sim models | Clifford Wolf | 2015-01-08 | 1 | -0/+150 | |
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* | More Xilinx bram cleanups | Clifford Wolf | 2015-01-07 | 1 | -14/+14 | |
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* | Cleanups in xilinx bram descriptions | Clifford Wolf | 2015-01-07 | 2 | -36/+36 | |
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* | Xilinx RAMB36/RAMB18 memory_bram support complete | Clifford Wolf | 2015-01-06 | 3 | -16/+320 | |
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* | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 3 | -24/+65 | |
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* | small fix in xilinx/brams.v | Clifford Wolf | 2015-01-06 | 1 | -5/+5 | |
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* | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 4 | -25/+176 | |
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* | Various small improvements to synth_xilinx | Clifford Wolf | 2015-01-06 | 1 | -8/+6 | |
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* | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 2 | -13/+41 | |
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* | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 3 | -6/+10 | |
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* | Towards Xilinx bram support | Clifford Wolf | 2015-01-05 | 7 | -19/+172 | |
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* | Towards Xilinx bram support | Clifford Wolf | 2015-01-04 | 3 | -13/+182 | |
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* | Progress in memory_bram | Clifford Wolf | 2014-12-31 | 1 | -3/+3 | |
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* | Added memory_bram (not functional yet) | Clifford Wolf | 2014-12-31 | 1 | -0/+20 | |
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* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+5 | |
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* | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 1 | -18/+18 | |
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* | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -2/+2 | |
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* | Added "techmap -share_map" option | Clifford Wolf | 2013-11-24 | 1 | -4/+4 | |
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* | Fixed xilinx/example_sim_counter test bench | Clifford Wolf | 2013-11-24 | 1 | -1/+1 | |
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* | Added more generic _TECHMAP_ wire mechanism to techmap pass | Clifford Wolf | 2013-11-23 | 1 | -1/+1 | |
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* | [EXAMPLES] Ported the mojo counter example to Zynq ZED board. | James Walmsley | 2013-10-27 | 4 | -0/+56 | |
| | | | | Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days. | |||||
* | Cleanups in xilinx examples | Clifford Wolf | 2013-10-27 | 3 | -144/+28 | |
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* | Added synth_xilinx command | Clifford Wolf | 2013-10-27 | 2 | -0/+219 | |
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* | Moved simple xilinx counter sim example to subdir | Clifford Wolf | 2013-10-27 | 3 | -0/+0 | |
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* | Xilinx mojo_counter example is now working | Clifford Wolf | 2013-10-27 | 3 | -4/+9 | |
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* | Renamed techlibs/xilinx7 to techlibs/xilinx | Clifford Wolf | 2013-10-26 | 8 | -0/+316 | |