| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 1 | -11/+42 |
| | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | ||||
| * | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk | Eddie Hung | 2020-02-06 | 1 | -4/+5 |
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| * | Fix/cleanup +/xilinx/arith_map.v | Eddie Hung | 2020-02-06 | 1 | -111/+44 |
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| * | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 | Eddie Hung | 2020-01-17 | 1 | -117/+82 |
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| * | +/xilinx/arith_map.v fix $lcu rule | Eddie Hung | 2020-01-17 | 1 | -6/+6 |
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| * | Instead of MUXCY/XORCY use CARRY4 (with timing) | Eddie Hung | 2019-05-21 | 1 | -2/+2 |
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| * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -7/+275 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+91 |
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index : iCE40/yosys | |
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