iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	1	-35/+45
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*	intel_alm: Documentation improvements	Dan Ravensloft	2020-04-21	1	-0/+69
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+482
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).