iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: M10K write-enable is negative-true	Lofty	2022-03-09	1	-0/+1
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*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	1	-0/+1
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	intel: move Cyclone V support to intel_alm	Dan Ravensloft	2020-08-20	1	-0/+2
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*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	1	-3/+3
\| \| \| \|	This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	1	-3/+3
\| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	1	-3/+3
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*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	1	-0/+2
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*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	1	-0/+3
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*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
*	intel_alm: cleanup duplication	Dan Ravensloft	2020-04-24	1	-3/+0
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+23
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).