| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells | Eddie Hung | 2020-05-14 | 1 | -0/+153 |
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| * | ice40: add synth_ice40 -dff option, support with -abc9 | Eddie Hung | 2020-05-14 | 1 | -0/+13 |
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| * | ice40: fix ICESTORM_LC process sensitivity | Eddie Hung | 2020-05-12 | 1 | -1/+1 |
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| * | ice40: Fix typos in SPRAM ABC9 timing specs | Sylvain Munaut | 2020-03-20 | 1 | -2/+2 |
| | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | ice40: Fix SPRAM model to keep data stable if chipselect is low | Sylvain Munaut | 2020-03-14 | 1 | -5/+8 |
| | | | | | | | | | According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | ice40: fix specify for ICE40_{LP,U} | Eddie Hung | 2020-03-05 | 1 | -4/+4 |
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| * | ice40: fix implicit signal in specify, also clamp negative times to 0 | Eddie Hung | 2020-03-04 | 1 | -22/+22 |
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| * | ice40: add delays to SB_CARRY | Eddie Hung | 2020-02-27 | 1 | -0/+30 |
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| * | More +/ice40/cells_sim.v fixes | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
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| * | ice40: fix specify for inverted clocks | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
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| * | ice40: specify fixes | Eddie Hung | 2020-02-27 | 1 | -54/+54 |
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| * | ice40: move over to specify blocks for -abc9 | Eddie Hung | 2020-02-27 | 1 | -85/+1283 |
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| * | ice40: add SB_SPRAM256KA arrival time | Eddie Hung | 2020-01-24 | 1 | -0/+1 |
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| * | ice40: Add post-pnr ICESTORM_RAM model and fix FFs | David Shah | 2019-10-23 | 1 | -2/+340 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40: Support for post-pnr timing simulation | David Shah | 2019-10-23 | 1 | -12/+96 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -79/+78 |
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| * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 1 | -28/+0 |
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| * | Comment out SB_MAC16 arrival time for now, need to handle all its modes | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | Add arrival for SB_MAC16.O | Eddie Hung | 2019-08-28 | 1 | -0/+1 |
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| * | Add arrival times for U | Eddie Hung | 2019-08-28 | 1 | -0/+26 |
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| * | Round not floor | Eddie Hung | 2019-08-28 | 1 | -21/+21 |
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| * | Add LP timings | Eddie Hung | 2019-08-28 | 1 | -0/+26 |
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| * | LX -> LP | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| | * | Trailing comma | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | | Add arrival times for HX devices | Eddie Hung | 2019-08-28 | 1 | -21/+114 |
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| * | Update to new $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -11/+8 |
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| * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -2/+4 |
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| * | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
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| * | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 1 | -2/+8 |
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| * | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
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| * | Add new box to cells_sim.v | Eddie Hung | 2019-07-12 | 1 | -2/+25 |
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| * | Remove noise from ice40/cells_sim.v | Eddie Hung | 2019-06-27 | 1 | -5/+0 |
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| * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -2/+2 |
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| * | Fix and cleanup ice40 boxes for carry in/out | Eddie Hung | 2019-06-22 | 1 | -2/+2 |
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| * | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 1 | -25/+25 |
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| * | Remove abc_flop{,_d} attributes from ice40/cells_sim.v | Eddie Hung | 2019-06-12 | 1 | -40/+20 |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-10 | 1 | -0/+24 |
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| | * | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 |
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| * | | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) | Eddie Hung | 2019-06-03 | 1 | -3/+3 |
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| * | | Consistent with xilinx | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
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| * | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -1/+1 |
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| | * | | Use nonblocking | Eddie Hung | 2019-04-23 | 1 | -1/+1 |
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| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 1 | -0/+11 |
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| | * | ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC | Sylvain Munaut | 2019-05-13 | 1 | -0/+11 |
| | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -10/+19 |
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| | * | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵ | Luke Wren | 2019-04-21 | 1 | -10/+19 |
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| * | | Convert to use #945 | Eddie Hung | 2019-04-21 | 1 | -8/+2 |
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index : iCE40/yosys | |
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