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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+9
| | | | Fixes #2058.
* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-241-2/+1
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
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* Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-1/+1
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* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-025-15/+18
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-015-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
|/ | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
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* attempt to fix formattingPepijn de Vos2019-11-251-154/+154
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* gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
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* gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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* Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | | | | The hardware does not actually support it. In reality it is always initialised to its reset value.
* add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
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* fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
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* fix wide lutsPepijn de Vos2019-11-061-12/+12
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* add IOBUFPepijn de Vos2019-10-282-1/+10
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* add tristate buffer and testPepijn de Vos2019-10-282-2/+8
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* More formattingPepijn de Vos2019-10-281-55/+49
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* really really fix formatting maybePepijn de Vos2019-10-281-41/+41
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* undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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* add wide lutsPepijn de Vos2019-10-283-36/+119
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* add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
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* ALU sim tweaksPepijn de Vos2019-10-241-11/+11
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* add a few more missing dffPepijn de Vos2019-10-211-7/+16
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* add negedge DFFPepijn de Vos2019-10-212-15/+139
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* use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
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* remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
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* Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| | | | | | It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
* fix BRAM width and initPepijn de Vos2019-09-062-12/+28
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* add more DFF to sim libPepijn de Vos2019-09-062-6/+111
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* WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
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* support bram initialisationPepijn de Vos2019-09-055-3/+25
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* use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
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* add MUX supportPepijn de Vos2019-09-053-0/+17
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* set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
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* Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| * Updating gowinDiego H2019-09-022-2/+2
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* | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
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* Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-2/+2
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* Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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| * GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flowDiego2019-04-1210-11/+459
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* | Make nobram false by default for gowinMiodrag Milanovic2019-04-021-1/+1
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* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-282-7/+7
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* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-3/+11
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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-034-4/+83
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