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* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-9/+1
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* synth_gowin: move splitnets to after iopadmap (#2435)Pepijn de Vos2021-11-071-2/+3
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* Remove noalu from synth_gowin json output as Apicula now supports itPepijn de Vos2021-11-071-1/+0
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* gowin: widelut support (#3042)Pepijn de Vos2021-11-061-1/+0
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* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-203-5/+12
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-082-2/+2
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
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* synth_gowin: Add rPLL blackboxKonrad Beckmann2020-11-111-0/+45
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* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-4/+4
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* gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-145/+41
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* synth_gowin: ABC9 supportDan Ravensloft2020-07-052-34/+340
| | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
|\ | | | | gowin: Fix INIT values in sim library.
| * gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
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* | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-25/+25
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* Use C++11 final/override keywords.whitequark2020-06-182-6/+6
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+9
| | | | Fixes #2058.
* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-241-2/+1
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
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* Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-1/+1
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* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-025-15/+18
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-015-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
|/ | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
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* attempt to fix formattingPepijn de Vos2019-11-251-154/+154
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* gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
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* gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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* Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | | | | The hardware does not actually support it. In reality it is always initialised to its reset value.
* add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
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* fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
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* fix wide lutsPepijn de Vos2019-11-061-12/+12
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* add IOBUFPepijn de Vos2019-10-282-1/+10
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* add tristate buffer and testPepijn de Vos2019-10-282-2/+8
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* More formattingPepijn de Vos2019-10-281-55/+49
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* really really fix formatting maybePepijn de Vos2019-10-281-41/+41
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* undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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* add wide lutsPepijn de Vos2019-10-283-36/+119
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* add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
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* ALU sim tweaksPepijn de Vos2019-10-241-11/+11
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* add a few more missing dffPepijn de Vos2019-10-211-7/+16
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* add negedge DFFPepijn de Vos2019-10-212-15/+139
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* use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
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* remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
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* Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| | | | | | It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
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