| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 1 | -0/+132 |
| | | | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode | ||||
| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 1 | -0/+128 |
| Signed-off-by: Patrick Urban <patrick.urban@web.de> | |||||
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index : iCE40/yosys | |
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