Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. | Marcelina Kościelnicka | 2022-06-02 | 1 | -2/+18 |
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* | ecp5: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 9 | -466/+584 |
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* | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 2 | -1/+2 |
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* | ecp5: Do not use specify in generate in cells_sim.v. | Marcelina Kościelnicka | 2022-02-21 | 1 | -28/+15 |
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* | ecp5: Fix DPR16X4 sim model. | Marcelina Kościelnicka | 2022-02-09 | 1 | -1/+1 |
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* | ecp5: Add support for mapping aldff. | Marcelina Kościelnicka | 2021-10-27 | 2 | -13/+13 |
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* | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -1/+1 |
| | | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review | ||||
* | [ECP5] fix wrong link for syn_* attributes description (#2984) | kittennbfive | 2021-08-29 | 2 | -2/+2 |
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* | Add DLLDELD | ECP5-PCIe | 2021-08-22 | 1 | -0/+9 |
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* | ecp5: Add DCSC blackbox | gatecat | 2021-07-06 | 1 | -0/+10 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Use HTTPS for website links, gatecat email | Claire Xenia Wolf | 2021-06-09 | 3 | -3/+3 |
| | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g; | ||||
* | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 3 | -4/+4 |
| | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
* | Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. | Adam Greig | 2021-05-12 | 1 | -0/+22 |
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* | Blackbox all whiteboxes after synthesis | gatecat | 2021-03-17 | 1 | -0/+1 |
| | | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 1 | -11/+15 |
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* | ecp5: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-05 | 4 | -254/+96 |
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* | Update dff2dffe, dff2dffs, zinit to new FF types. | Marcelina Kościelnicka | 2020-06-23 | 2 | -31/+31 |
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* | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 3 | -9/+9 |
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* | ecp5: cleanup unused +/ecp5/abc9_model.v | Eddie Hung | 2020-05-23 | 3 | -14/+0 |
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* | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 2 | -0/+11 |
| | | | | Fixes #2058. | ||||
* | ecp5: latches_map.v if *not* -asyncprld | Eddie Hung | 2020-05-14 | 1 | -2/+2 |
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* | ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v | Eddie Hung | 2020-05-14 | 4 | -43/+3 |
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* | ecp5: fix rebase mistake | Eddie Hung | 2020-05-14 | 1 | -3/+3 |
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* | ecp5: TRELLIS_FF bypass path only in async mode | Eddie Hung | 2020-05-14 | 1 | -8/+8 |
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* | xilinx/ice40/ecp5: zinit requires selected wires, so select them all | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
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* | xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells | Eddie Hung | 2020-05-14 | 1 | -3/+26 |
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* | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
| | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier | ||||
* | synth_*: no need to explicitly read +/abc9_model.v | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
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* | Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" | Eddie Hung | 2020-05-14 | 3 | -220/+64 |
| | | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b. | ||||
* | ecp5: (* abc9_flop *) gated behind YOSYS | Eddie Hung | 2020-05-14 | 1 | -0/+2 |
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* | ecp5: add synth_ecp5 -dff to work with -abc9 | Eddie Hung | 2020-05-14 | 2 | -12/+47 |
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* | ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init | Eddie Hung | 2020-05-14 | 3 | -64/+220 |
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* | ecp5: Add missing SERDES parameters | David Shah | 2020-05-12 | 1 | -0/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad | Eddie Hung | 2020-05-04 | 1 | -0/+13 |
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* | gowin,ecp5: remove generated files in `make clean`. | whitequark | 2020-04-24 | 1 | -0/+9 |
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* | ecp5: ecp5_gsr to skip cells that don't have GSR parameter again | Eddie Hung | 2020-04-22 | 1 | -1/+1 |
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* | Cleanup use of hard-coded default parameters in light of #1945 | Eddie Hung | 2020-04-22 | 2 | -12/+6 |
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* | ecp5: Force SIGNED ports to be 1 bit | David Shah | 2020-04-16 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Get rid of dffsr2dff. | Marcelina Kościelnicka | 2020-04-15 | 1 | -1/+0 |
| | | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed. | ||||
* | Merge pull request #1603 from whitequark/ice40-ram_style | whitequark | 2020-04-10 | 3 | -1/+74 |
|\ | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes | ||||
| * | ecp5: do not map FFRAM if explicitly requested otherwise. | whitequark | 2020-04-03 | 1 | -1/+3 |
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| * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. | whitequark | 2020-02-06 | 2 | -0/+71 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires). | ||||
* | | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 2 | -24/+24 |
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* | | Merge pull request #1716 from zeldin/ecp5_fix | N. Engelhardt | 2020-03-09 | 1 | -2/+0 |
|\ \ | | | | | | | ecp5: remove unused parameter from \$__ECP5_PDPW16KD | ||||
| * | | remove unused parameters | N. Engelhardt | 2020-03-06 | 1 | -3/+0 |
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| * | | ecp5: Add missing parameter to \$__ECP5_PDPW16KD | Marcus Comstedt | 2020-02-22 | 1 | -0/+1 |
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* | | synth_ecp5: use +/abc9_model.v | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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* | | ecp5: remove small LUT entries | Eddie Hung | 2020-02-27 | 1 | -24/+6 |
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* | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box} | Eddie Hung | 2020-02-27 | 7 | -86/+120 |
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* | synth_*: call 'opt -fast' after 'techmap' | Eddie Hung | 2020-02-05 | 1 | -0/+1 |
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