| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -83/+83 |
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| * | coolrunner2: Attempt to give wires/cells more meaningful names | R. Ou | 2020-03-02 | 1 | -17/+48 |
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| * | coolrunner2: Fix invalid multiple fanouts of XOR/OR gates | R. Ou | 2020-03-02 | 1 | -0/+96 |
| | | | | | | | | | | | | | | | | | | | | | | | | In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule | ||||
| * | coolrunner2: Fix packed register+input buffer insertion | R. Ou | 2020-03-02 | 1 | -2/+84 |
| | | | | | | The register will be packed with the input buffer if and only if the input buffer doesn't have any other loads. | ||||
| * | coolrunner2: Insert many more required feedthrough cells | R. Ou | 2020-03-01 | 1 | -36/+186 |
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| * | coolrunner2: Separate and improve buffer cell insertion pass | R. Ou | 2020-02-16 | 1 | -0/+161 |
| The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between. | |||||
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index : iCE40/yosys | |
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