| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Revert "Leave only real black box cells" | Icenowy Zheng | 2018-12-17 | 1 | -0/+312 |
| | | | | | | | | | | | | This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | ||||
| * | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 |
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| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 1 | -0/+1028 |
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index : iCE40/yosys | |
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