| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -2/+2 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 1 | -0/+9 |
| | | | | | Fixes #2058. | ||||
| * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 1 | -17/+25 |
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| * | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 |
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| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 1 | -0/+84 |
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index : iCE40/yosys | |
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