iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Fixed dfflibmap for cell libraries with no set-reset-ff	Clifford Wolf	2014-02-15	1	-1/+1
*	Fixed opt_const handling of double invert with non-1 output width	Clifford Wolf	2014-02-15	1	-1/+1
*	Added abc -keepff option	Clifford Wolf	2014-02-14	1	-5/+18
*	updated default ABC command strings	Clifford Wolf	2014-02-13	1	-4/+4
*	Updated ABC	Clifford Wolf	2014-02-13	1	-0/+23
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-7/+19
*	Removed double blanks in ABC default command sequences	Clifford Wolf	2014-02-13	1	-4/+4
*	Updated ABC and some related changes	Clifford Wolf	2014-02-13	1	-10/+31
*	Updated ABC to rev e97a6e1d59b9	Clifford Wolf	2014-02-12	1	-4/+49
*	Various improvements in expose command (added -sep and -cut)	Clifford Wolf	2014-02-09	1	-36/+119
*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09	1	-5/+36
*	Bugfix in delete command	Clifford Wolf	2014-02-09	1	-1/+3
*	Fixed handling of async reset in expose -evert-dff	Clifford Wolf	2014-02-08	1	-0/+1
*	Build fixes for log cmd	Clifford Wolf	2014-02-08	1	-2/+2
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-08	2	-0/+79
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\| *	added "log" command	Johann Glaser	2014-02-08	2	-0/+79
* \|	Implemented expose -evert-dff	Clifford Wolf	2014-02-08	1	-11/+301
* \|	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08	1	-0/+1
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*	Added various new options to splice command	Clifford Wolf	2014-02-08	1	-5/+105
*	Added %a select operator	Clifford Wolf	2014-02-08	1	-0/+32
*	Moved some passes to other source directories	Clifford Wolf	2014-02-08	9	-9/+3
*	Added support for "keep" attribute to abc pass	Clifford Wolf	2014-02-08	1	-1/+1
*	Added opt -purge (frontend to opt_clean -purge)	Clifford Wolf	2014-02-08	1	-3/+8
*	Only count non-trivial attributes when findinf master signal in opt_clean	Clifford Wolf	2014-02-08	1	-2/+13
*	Now also move net labes to the right position in splice cmd	Clifford Wolf	2014-02-08	1	-3/+10
*	Improved detection of primary wire for a signal in opt_clean	Clifford Wolf	2014-02-07	1	-4/+23
*	Added splice command	Clifford Wolf	2014-02-07	2	-0/+253
*	Added log_header() to splitnets	Clifford Wolf	2014-02-07	1	-0/+2
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+18
*	Re-enabled abc "retime" after sorting yout the yosys-bigsim problem	Clifford Wolf	2014-02-07	1	-7/+0
*	Fixed use of "cmd_error" in passes/cmds/design.cc	Clifford Wolf	2014-02-07	1	-2/+2
*	Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim fa...	Clifford Wolf	2014-02-06	1	-0/+7
*	Added "retime" to standard ABC recipes	Clifford Wolf	2014-02-06	1	-4/+4
*	Added copy command	Clifford Wolf	2014-02-06	2	-0/+55
*	Added design -stash/-copy-from/-copy-to	Clifford Wolf	2014-02-06	1	-13/+99
*	Added support for s: select expressions (wire width)	Clifford Wolf	2014-02-06	1	-1/+21
*	Added i:, o:, and x: selection pattern	Clifford Wolf	2014-02-06	1	-0/+18
*	Added support for %m selection op	Clifford Wolf	2014-02-06	1	-0/+16
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-06	1	-0/+25
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\| *	new %s: add sub-modules to selection	Johann Glaser	2014-02-06	1	-0/+25
* \|	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	3	-37/+20
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*	Added support for sat -show @<sel_name>	Clifford Wolf	2014-02-06	1	-0/+17
*	Added sat -set-init-def and sat -tempinduct-def	Clifford Wolf	2014-02-06	1	-4/+34
*	Added opt_const -undriven	Clifford Wolf	2014-02-06	2	-3/+68
*	Added expose -dff	Clifford Wolf	2014-02-06	1	-1/+44
*	Changed techmap description from "simple" to "generic"	Clifford Wolf	2014-02-06	1	-1/+1
*	Added miter -make_outcmp	Clifford Wolf	2014-02-06	1	-2/+23
*	Added sat -set-init-zero support	Clifford Wolf	2014-02-06	1	-2/+22
*	Added sat -verify and -falsify support for non-prove cases	Clifford Wolf	2014-02-06	1	-14/+26
*	Added expose command	Clifford Wolf	2014-02-05	2	-0/+264