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| | * | | | | | | | | | | | | | | | | | Fix port hanlding in pmgenClifford Wolf2019-08-231-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | | | | | | | | | | Add pmgen slices and choicesClifford Wolf2019-08-234-28/+276
| | |/ / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | clkbufmap to only check clkbuf_inhibit if no selection givenEddie Hung2019-08-231-5/+18
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| * | | | | | | | | | | | | | | | | | Review comment from @cliffordwolfEddie Hung2019-08-231-1/+2
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| * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-2348-768/+2262
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| | * | | | | | | | | | | | | | | | | SpellingEddie Hung2019-08-221-2/+2
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| | * | | | | | | | | | | | | | | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftxEddie Hung2019-08-221-4/+26
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | opt_expr to trim A port of $shiftx/$shift
| | | * | | | | | | | | | | | | | | Copy-paste typoEddie Hung2019-08-221-1/+1
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| | | * | | | | | | | | | | | | | | Respect opt_expr -keepdc as per @cliffordwolfEddie Hung2019-08-221-1/+1
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| | | * | | | | | | | | | | | | | | Handle $shift and Y_WIDTH > 1 as per @cliffordwolfEddie Hung2019-08-221-4/+8
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| | | * | | | | | | | | | | | | | | Add cover()Eddie Hung2019-08-221-0/+1
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| | | * | | | | | | | | | | | | | | Canonical formEddie Hung2019-08-221-5/+5
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| | | * | | | | | | | | | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1Eddie Hung2019-08-211-0/+17
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| | * / / / / / / / / / / / / / / Fix test_pmgen depsMiodrag Milanovic2019-08-211-1/+1
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| | * | | | | | | | | | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmapClifford Wolf2019-08-211-4/+6
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | |/ / / / / / / / / / / / | | | |/| / / / / / / / / / / / | | | |_|/ / / / / / / / / / / | | |/| | | | | | | | | | | | techmap -max_iter to apply to each module individually
| | | * | | | | | | | | | | | GrammarEddie Hung2019-08-201-1/+1
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| | | * | | | | | | | | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
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| | * / | | | | | | | | | | Fix copy-paste typoEddie Hung2019-08-201-1/+1
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| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1641-2157/+2152
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| * | | | | | | | | | | | | move attributes to wiresMarcin Kościelnicki2019-08-132-28/+9
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| * | | | | | | | | | | | | review fixesMarcin Kościelnicki2019-08-132-29/+4
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| * | | | | | | | | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-133-20/+356
| | |_|_|_|_|_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | | | | | | | | | | Revert "Remove sequential extension"Eddie Hung2019-08-201-20/+68
| |_|_|/ / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.
* | | | | | | | | | | | Remove sequential extensionEddie Hung2019-08-201-68/+20
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* | | | | | | | | | | | retime_mode -> dff_modeEddie Hung2019-08-201-7/+7
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* | | | | | | | | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXMEEddie Hung2019-08-201-65/+13
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* | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-2011-101/+770
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| * | | | | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-201-43/+80
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes
| | * | | | | | | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-6/+6
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| * | | | | | | | | | | | Merge branch 'master' into clifford/pmgenClifford Wolf2019-08-204-36/+33
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| | * \ \ \ \ \ \ \ \ \ \ \ Merge pull request #1309 from whitequark/proc_clean-fix-1268whitequark2019-08-201-2/+1
| | |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | proc_clean: fix order of switch insertion
| | | * | | | | | | | | | | | proc_clean: fix order of switch insertion.whitequark2019-08-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1268.
| * | | | | | | | | | | | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgenClifford Wolf2019-08-1947-1514/+2270
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| * | | | | | | | | | | | | | | Refactor pmgen rollback mechanismClifford Wolf2019-08-171-32/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Improvements in "test_pmgen -generate"Clifford Wolf2019-08-171-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Add pmgen "fallthrough" statementClifford Wolf2019-08-172-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Add help() callEddie Hung2019-08-161-0/+1
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| * | | | | | | | | | | | | | | Minor bugfix in "test_pmgen -generate"Clifford Wolf2019-08-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Add pmgen finish statement, return number of matchesClifford Wolf2019-08-164-82/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Redesign pmgen backtracking for recursive matchingClifford Wolf2019-08-162-33/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Add pmgen "generate" featureClifford Wolf2019-08-163-13/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Refactor demo_reduce into test_pmgenClifford Wolf2019-08-164-14/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOGClifford Wolf2019-08-151-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Update pmgen documentationClifford Wolf2019-08-151-4/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Change pmgen default rule to reject, switch peepopt behavior to acceptClifford Wolf2019-08-155-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Add demo_reduce pass to demonstrace recursive pattern matchingClifford Wolf2019-08-154-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | Improvements in pmgen for recursive patternsClifford Wolf2019-08-154-26/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-193-33/+32
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| * | | | | | | | | | | | | | | Fix typoEddie Hung2019-08-191-1/+1
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| * | | | | | | | | | | | | | | ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.ccEddie Hung2019-08-191-30/+30
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generated by cgit v1.2.3 (git 2.25.1) at 2025-06-20 17:48:59 +0000