| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Renamed "aig" to "aigmap" | Clifford Wolf | 2015-06-10 | 1 | -4/+4 | |
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| * | Fixed cellaigs port extending | Clifford Wolf | 2015-06-10 | 1 | -0/+7 | |
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| * | Replaced ezDefaultSAT with ezSatPtr | Clifford Wolf | 2015-02-21 | 2 | -17/+17 | |
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| * | Some test related fixes | Clifford Wolf | 2015-02-12 | 1 | -1/+1 | |
| | | | | | (incl. removal of three bad test cases) | |||||
| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 1 | -2/+2 | |
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| * | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 1 | -12/+12 | |
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| * | Added "test_cell -muxdiv" | Clifford Wolf | 2014-12-25 | 1 | -2/+18 | |
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| * | Added "test_cell -w" feature | Clifford Wolf | 2014-12-25 | 1 | -18/+39 | |
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| * | Fixed typo in test_cell | Clifford Wolf | 2014-10-18 | 1 | -1/+1 | |
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| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 3 | -44/+44 | |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 3 | -0/+9 | |
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| * | Added "test_abcloop" command | Clifford Wolf | 2014-09-19 | 2 | -0/+286 | |
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| * | Added $lcu cell type | Clifford Wolf | 2014-09-08 | 1 | -1/+26 | |
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| * | Added "$fa" cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+31 | |
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| * | Added "test_cell -const" | Clifford Wolf | 2014-09-08 | 1 | -2/+45 | |
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| * | Added "test_cell -nosat" | Clifford Wolf | 2014-09-07 | 1 | -59/+73 | |
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| * | Various bug fixes (related to $macc model testing) | Clifford Wolf | 2014-09-06 | 1 | -1/+1 | |
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| * | Added $macc SAT model | Clifford Wolf | 2014-09-06 | 1 | -5/+6 | |
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| * | Added $macc cell type | Clifford Wolf | 2014-09-06 | 1 | -2/+53 | |
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| * | Added "test_cell -script" | Clifford Wolf | 2014-09-06 | 1 | -1/+8 | |
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| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+0 | |
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| * | Fixed "test_cells -vlog" | Clifford Wolf | 2014-09-03 | 1 | -4/+6 | |
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| * | Improvements in "test_cell -vlog" | Clifford Wolf | 2014-09-02 | 1 | -3/+8 | |
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| * | Added test_cell -vlog | Clifford Wolf | 2014-09-02 | 1 | -2/+79 | |
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| * | Added SAT testing to test_cell eval stage | Clifford Wolf | 2014-09-02 | 1 | -1/+89 | |
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| * | Added $alu support to test_cell | Clifford Wolf | 2014-09-01 | 1 | -1/+22 | |
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| * | Added "test_cell -simlib -v" | Clifford Wolf | 2014-09-01 | 1 | -8/+29 | |
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| * | Added eval testing to test_cell | Clifford Wolf | 2014-08-31 | 1 | -0/+88 | |
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| * | Added $lut support in test_cell, techmap, satgen | Clifford Wolf | 2014-08-31 | 1 | -5/+28 | |
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| * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -93/+93 | |
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| * | Added "test_cell -s <seed>" | Clifford Wolf | 2014-08-16 | 1 | -5/+17 | |
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| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+0 | |
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| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -22/+22 | |
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| * | Added "test_autotb -n <num_iter>" option | Clifford Wolf | 2014-08-01 | 1 | -9/+27 | |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -3/+3 | |
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| * | Added "techmap -assert" | Clifford Wolf | 2014-07-31 | 1 | -1/+1 | |
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| * | Improvements in test_cell | Clifford Wolf | 2014-07-30 | 1 | -35/+89 | |
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| * | Added "test_cell" command | Clifford Wolf | 2014-07-29 | 2 | -0/+185 | |
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| * | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 2 | -0/+338 | |
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index : iCE40/yosys | |
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