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* Renamed "aig" to "aigmap"Clifford Wolf2015-06-101-4/+4
* Fixed cellaigs port extendingClifford Wolf2015-06-101-0/+7
* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-212-17/+17
* Some test related fixesClifford Wolf2015-02-121-1/+1
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-2/+2
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-12/+12
* Added "test_cell -muxdiv"Clifford Wolf2014-12-251-2/+18
* Added "test_cell -w" featureClifford Wolf2014-12-251-18/+39
* Fixed typo in test_cellClifford Wolf2014-10-181-1/+1
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-103-44/+44
* namespace YosysClifford Wolf2014-09-273-0/+9
* Added "test_abcloop" commandClifford Wolf2014-09-192-0/+286
* Added $lcu cell typeClifford Wolf2014-09-081-1/+26
* Added "$fa" cell typeClifford Wolf2014-09-081-0/+31
* Added "test_cell -const"Clifford Wolf2014-09-081-2/+45
* Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+1
* Added $macc SAT modelClifford Wolf2014-09-061-5/+6
* Added $macc cell typeClifford Wolf2014-09-061-2/+53
* Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+0
* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
* Added eval testing to test_cellClifford Wolf2014-08-311-0/+88
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-5/+28
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-93/+93
* Added "test_cell -s <seed>"Clifford Wolf2014-08-161-5/+17
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+0
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-22/+22
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-011-9/+27
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-3/+3
* Added "techmap -assert"Clifford Wolf2014-07-311-1/+1
* Improvements in test_cellClifford Wolf2014-07-301-35/+89
* Added "test_cell" commandClifford Wolf2014-07-292-0/+185
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-292-0/+338