iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
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*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
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*	Added eval testing to test_cell	Clifford Wolf	2014-08-31	1	-0/+88
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*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-5/+28
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*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-93/+93
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*	Added "test_cell -s <seed>"	Clifford Wolf	2014-08-16	1	-5/+17
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+0
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-22/+22
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*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-9/+27
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-3/+3
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31	1	-1/+1
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*	Improvements in test_cell	Clifford Wolf	2014-07-30	1	-35/+89
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*	Added "test_cell" command	Clifford Wolf	2014-07-29	2	-0/+185
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	2	-0/+338