iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02	1	-3/+8
*	Added test_cell -vlog	Clifford Wolf	2014-09-02	1	-2/+79
*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02	1	-1/+89
*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
*	Added eval testing to test_cell	Clifford Wolf	2014-08-31	1	-0/+88
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-5/+28
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-93/+93
*	Added "test_cell -s <seed>"	Clifford Wolf	2014-08-16	1	-5/+17
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+0
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-22/+22
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-9/+27
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-3/+3
*	Added "techmap -assert"	Clifford Wolf	2014-07-31	1	-1/+1
*	Improvements in test_cell	Clifford Wolf	2014-07-30	1	-35/+89
*	Added "test_cell" command	Clifford Wolf	2014-07-29	2	-0/+185
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	2	-0/+338