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* | Remove irrelevant citationsEddie Hung2019-02-211-8/+0
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* | Add attributionEddie Hung2019-02-211-0/+1
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* | abc9 to not select anything extra, and pop selection after final cleanEddie Hung2019-02-211-14/+2
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* | abc9 to write_xaiger -symbols, not -mapEddie Hung2019-02-211-3/+2
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* | Merge branch 'read_aiger' into xaigEddie Hung2019-02-211-2/+0
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* | abc9 to use &mfsEddie Hung2019-02-211-1/+2
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* | abc9 to only disconnect output ports of AND and NOT gatesEddie Hung2019-02-211-2/+4
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* | ABC -> ABC9Eddie Hung2019-02-201-1/+1
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* | abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_Eddie Hung2019-02-201-21/+29
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* | lut/not/and suffix to be ${lut,not,and}Eddie Hung2019-02-201-4/+4
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* | abc9 to cope with multiple modulesEddie Hung2019-02-201-7/+11
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* | abc9 to use & syntax for -fast, and name fixesEddie Hung2019-02-201-5/+5
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* | abc9 to cope with indexed wires when creating $lut from $_NOT_Eddie Hung2019-02-191-1/+6
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* | abc9 to replace $_NOT_ with $lutEddie Hung2019-02-191-4/+39
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* | Get rid of debugging stuff in abc9Eddie Hung2019-02-161-6/+1
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* | abc9 to write_aiger with -O option, and ignore dummy outputsEddie Hung2019-02-161-2/+8
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* | abc9 to handle comb loops, cope with constant outputs, disconnect using new wireEddie Hung2019-02-161-4/+67
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* | abc9 to cope with non-wideports, count cells properlyEddie Hung2019-02-161-11/+54
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* | Move lookup inside ifEddie Hung2019-02-151-2/+2
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* | RefactorEddie Hung2019-02-151-29/+32
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* | Cope with width != 1 when re-mapping cellsEddie Hung2019-02-151-11/+25
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* | abc9 to stitch results with CI/CO properlyEddie Hung2019-02-151-16/+32
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* | Fix stitchingEddie Hung2019-02-131-4/+4
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* | Merge remote-tracking branch 'origin/read_aiger' into xaigEddie Hung2019-02-131-0/+2
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| * | Missing headers for Xcode?Eddie Hung2019-02-121-0/+2
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* | Rip out some more stuffEddie Hung2019-02-131-36/+0
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* | Rip out unused functions in abc9Eddie Hung2019-02-121-416/+61
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* | WIP for ABC with aigerEddie Hung2019-02-121-130/+19
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* | Compile abc9Eddie Hung2019-02-082-8/+9
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* | Copy abc.cc to abc9.ccEddie Hung2019-02-081-0/+1868
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* flowmap: clean up terminology.whitequark2019-01-081-17/+18
| | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
* flowmap: implement depth relaxation.whitequark2019-01-081-22/+680
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* flowmap: construct a max-volume max-flow min-cut, not just any one.whitequark2019-01-061-7/+10
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* flowmap: add -minlut option, to allow postprocessing with opt_lut.whitequark2019-01-041-7/+21
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* flowmap: cleanup for clarity. NFCI.whitequark2019-01-041-107/+141
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* flowmap: improve debug graph output. NFC.whitequark2019-01-041-47/+76
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* flowmap: add link to longer version of paper. NFC.whitequark2019-01-041-2/+3
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* flowmap: new techmap pass.whitequark2019-01-032-0/+874
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* Add "dffinit -noreinit" parameterIcenowy Zheng2018-12-181-1/+14
| | | | | | | | | | | | | | | Sometimes the FF cell might be initialized during the map process, e.g. some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has only a "SR" pin for a FF for async reset, that resets the FF to the initial value, which means the async reset value should be set as the initial value. In this case the DFFINIT pass shouldn't reinitialize it to a different value, which will lead to error. Add a "-noreinit" parameter for the safeguard. If a FF is not technically initialized before DFFINIT pass, the default value should be set to x. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Add "dffinit -strinit high low"Icenowy Zheng2018-12-181-2/+16
| | | | | | | | | | On some platforms the string to initialize DFF might not be "high" and "low", e.g. with Anlogic TD it's "SET" and "RESET". Add a "-strinit" parameter for dffinit to allow specify the strings used for high and low. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Revert "Proof-of-concept: preserve naming through ABC using dress"Clifford Wolf2018-12-161-51/+29
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* Merge pull request #735 from daveshah1/trifixesClifford Wolf2018-12-161-3/+4
|\ | | | | deminout fixes
| * deminout: Consider $tribuf cellsDavid Shah2018-12-121-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * deminout: Don't demote constant-driven inouts to inputsDavid Shah2018-12-121-1/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #714 from daveshah1/abc_preserve_namingClifford Wolf2018-12-161-29/+51
|\ \ | | | | | | Proof-of-concept: preserve naming through ABC using dress
| * | abc: Preserve naming through ABC using 'dress' commandDavid Shah2018-12-061-29/+51
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / lut2mux: handle 1-bit INIT constant in $lut cells.whitequark2018-12-051-1/+1
|/ | | | | This pass already handles INIT constants shorter than 2^width, but that was not done for the recursion base case.
* Fix typoClifford Wolf2018-12-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* dff2dffe: Add option for unmap to only remove DFFE with low CE signal useSylvain Munaut2018-11-271-1/+36
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* DFFLIBMAP: changed 'missing pin' error into a warning with additional ↵Niels Moseley2018-11-061-1/+10
| | | | reason/info.