iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Bugfix in mapping $tribuf to $_TBUF_	Clifford Wolf	2015-11-05	1	-1/+1
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
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*	Added $tribuf and $_TBUF_ cell types	Clifford Wolf	2015-08-16	1	-1/+17
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-6/+6
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*	Added simplemap $lut support	Clifford Wolf	2015-04-27	1	-0/+24
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*	Improved attributes API and handling of "src" attributes	Clifford Wolf	2015-04-24	1	-4/+22
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*	Fixed simplemap for $ne cells with output width > 1	Clifford Wolf	2014-12-25	1	-7/+8
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*	Improvements in simplemap api, added $ne $nex $eq $eqx support	Clifford Wolf	2014-12-24	1	-23/+58
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Added $dffe cell type	Clifford Wolf	2014-12-08	1	-0/+23
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-9/+9
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-1/+11
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-12/+1
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-4/+4
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-3/+3
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-85/+85
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-11/+9
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-5/+5
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-99/+99
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-99/+99
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-60/+16
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-98/+45
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-56/+56
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-56/+56
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-4/+4
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+18
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*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29	1	-2/+2
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*	Added new cell types to manual	Clifford Wolf	2013-12-28	1	-1/+1
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-0/+13
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-25/+30
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*	Added simplemap pass	Clifford Wolf	2013-11-24	1	-0/+517