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* iopadmap: Fix z assignment removal.Marcelina Kościelnicka2022-06-071-7/+21
| | | | Fixes #3360.
* Correct a typo in the manualYRabbit2022-02-021-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* iopadmap: Fix ebmarassing typoMarcelina Kościelnicka2021-11-101-1/+1
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* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-7/+22
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-021-4/+4
|\ | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-4/+4
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* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+15
|/ | | | Fixes #1841.
* iopadmap: Attempt to give new wires/cells meaningful namesR. Ou2020-03-221-6/+18
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* iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-14/+54
| | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* iopadmap: fixes as suggested by @mwkmwkmwkEddie Hung2020-02-131-19/+11
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* iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-3/+20
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* take skip wire bits into accountMiodrag Milanovic2020-01-011-0/+3
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* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-23/+68
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* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-146/+97
| | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
* Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-6/+6
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| * Use ID::keep more liberally tooEddie Hung2019-08-151-4/+4
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| * Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-2/+2
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* | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-161-8/+8
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| * ID(\\.*) -> ID(.*)Eddie Hung2019-08-151-7/+7
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| * Transform all "\\*" identifiers into ID()Eddie Hung2019-08-151-7/+7
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| * Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-151-1/+1
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* | move attributes to wiresMarcin Kościelnicki2019-08-131-9/+4
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* | review fixesMarcin Kościelnicki2019-08-131-14/+1
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* | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-20/+56
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Fix iopadmap for loops between tristate IO buffersClifford Wolf2018-05-151-0/+21
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix iopadmap for cases where IO pins already have buffers on themClifford Wolf2018-05-151-1/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Undo "preserve wire attributes in iopadmap" change (it was OK before)Clifford Wolf2016-08-081-1/+1
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* preserve wire attributes in iopadmapClifford Wolf2016-08-061-1/+1
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* Added tristate buffer support to iopadmapClifford Wolf2016-05-041-4/+161
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* Fixed iopadmap attribute handlingClifford Wolf2016-05-041-0/+1
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Fixed iopadmap help messageClifford Wolf2015-08-311-3/+3
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Bugfix in iopadmapClifford Wolf2015-02-251-10/+3
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* Various small improvements to synth_xilinxClifford Wolf2015-01-061-2/+2
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* namespace YosysClifford Wolf2014-09-271-1/+5
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* Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-4/+4
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
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* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-7/+2
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-4/+4
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-4/+4
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+2
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-2/+2
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-2/+2
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