iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-12/+3
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+9
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-15/+15
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-15/+15
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-14/+3
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Fixed memory corruption with new SigSpec API in proc_mux	Clifford Wolf	2014-07-22	1	-7/+3
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-22/+22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-22/+22
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*	Tiny cleanup in proc_mux.cc	Clifford Wolf	2014-01-03	1	-3/+0
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*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-1/+1
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*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01	1	-3/+15
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+294