iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	proc_mux: consider \src attribute on CaseRule.	whitequark	2019-07-08	1	-10/+16
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*	Improve proc full_case detection and handling, fixes #931	Clifford Wolf	2019-04-18	1	-0/+50
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Revert #895	Eddie Hung	2019-04-16	1	-28/+0
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*	proc_mux: Fix crash when trying to optimize non-existant mux to shiftx	Sylvain Munaut	2019-04-03	1	-1/+1
\| \| \| \| \| \|	last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
*	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
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*	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
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*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	1	-17/+31
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*	Fixed proc_mux performance bug	Clifford Wolf	2016-04-25	1	-0/+3
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Improved proc_mux performance for huge always blocks	Clifford Wolf	2015-12-02	1	-36/+153
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-7/+11
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-15/+15
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+2
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-7/+6
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-5/+5
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-12/+3
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+9
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-15/+15
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-15/+15
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-14/+3
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Fixed memory corruption with new SigSpec API in proc_mux	Clifford Wolf	2014-07-22	1	-7/+3
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-22/+22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-22/+22
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*	Tiny cleanup in proc_mux.cc	Clifford Wolf	2014-01-03	1	-3/+0
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*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-1/+1
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*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01	1	-3/+15
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+294