| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | proc_prune: promote assigns to module connections when legal. | whitequark | 2019-07-09 | 1 | -20/+6 |
| | | | | | | | | | | | This can pave the way for further transformations by exposing identities that were previously hidden in a process to any pass that uses SigMap. Indeed, this commit removes some ad-hoc logic from proc_init that appears to have been tailored to the output of genrtlil in favor of using `SigMap.apply()`. (This removal is not optional, as the ad-hoc logic cannot cope with the result of running proc_prune; a similar issue was fixed in proc_arst.) | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | More flexible handling of initialization values | Clifford Wolf | 2016-04-22 | 1 | -7/+22 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Re-created command-reference-manual.tex, copied some doc fixes to online help | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -2/+6 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+1 |
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| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -10/+9 |
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| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -2/+0 |
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| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -6/+6 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -6/+6 |
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| * | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 | 1 | -0/+114 |
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index : iCE40/yosys | |
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