iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-39/+39
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-10/+3
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*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25	1	-5/+7
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-17/+19
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-14/+14
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-14/+14
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*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21	1	-5/+19
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*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18	1	-0/+15
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*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17	1	-5/+18
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*	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16	1	-0/+80
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*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12	1	-1/+4
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*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06	1	-2/+2
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-0/+1
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*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01	1	-1/+16
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+236