iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixed off-by-one bug in "hierarchy -check" for positional module args	Clifford Wolf	2014-12-24	1	-2/+2
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*	Checking existence of ports in "hierarchy -check"	Clifford Wolf	2014-12-19	1	-0/+13
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*	Fixed bug in "hierarchy -top" with array of instances	Clifford Wolf	2014-11-27	1	-3/+10
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*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17	1	-2/+2
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*	Header changes so it will compile on VS	William Speirs	2014-10-17	1	-1/+5
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*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	1	-1/+1
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*	Moved patmatch() to yosys.cc	Clifford Wolf	2014-10-10	1	-1/+0
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*	Replaced fnmatch() with patmatch()	Clifford Wolf	2014-10-10	1	-5/+4
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*	set "keep" on modules with $assert cells in "hierarchy"	Clifford Wolf	2014-09-30	1	-0/+30
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-11/+13
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*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-4/+4
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*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+2
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-15/+15
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29	1	-1/+3
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+2
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-30/+30
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-5/+5
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-4/+4
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-4/+1
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+2
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-5/+5
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-5/+5
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
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*	fixed cell array handling of positional arguments	Clifford Wolf	2014-06-07	1	-2/+11
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*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+34
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-7/+19
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*	Added hierarchy -purge_lib option	Clifford Wolf	2014-02-04	1	-3/+14
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*	Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))	Martin Schmölzer	2014-01-14	1	-0/+1
\| \| \| \| \| \|	This fixes compilation errors on Arch Linux. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
*	Added hierarchy -libdir option	Clifford Wolf	2014-01-14	1	-4/+48
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-60/+0
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-0/+17
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-3/+3
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*	Added resolution of positional arguments to hierarchy pass	Clifford Wolf	2013-11-03	1	-0/+57
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*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-2/+2
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*	Improved log messages generated by hierarchy pass	Clifford Wolf	2013-05-26	1	-5/+17
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*	Fixed hierarchy pass for hierarchies of parametric modules	Clifford Wolf	2013-04-26	1	-0/+1
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-2/+5
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*	Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	2013-03-26	1	-1/+8
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*	Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	2013-03-25	1	-1/+165
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*	Implemented general handler for selection arguments	Clifford Wolf	2013-03-03	1	-1/+2
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*	Added online help for "show" and "hierarchy" commands	Clifford Wolf	2013-02-28	1	-3/+25
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+194