| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $alu to list of supported cells for "stat -width" | Clifford Wolf | 2017-07-14 | 1 | -1/+1 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Added "stat -liberty" for calculating chip area | Clifford Wolf | 2016-02-04 | 1 | -6/+60 |
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| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
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| * | improvement in "stat" | Clifford Wolf | 2015-10-24 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Fixed "stat" handling of blackbox modules | Clifford Wolf | 2015-02-14 | 1 | -9/+6 |
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| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -5/+5 |
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| * | sort cell types in "stat" output by name | Clifford Wolf | 2014-10-03 | 1 | -2/+2 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -113/+114 |
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| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+1 |
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| * | Added "stat -width" | Clifford Wolf | 2014-08-22 | 1 | -4/+37 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Bugfixes in new "stat" command | Clifford Wolf | 2013-11-25 | 1 | -7/+1 |
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| * | Added "stat" command | Clifford Wolf | 2013-11-25 | 1 | -0/+218 |
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index : iCE40/yosys | |
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