iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-2/+2
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-4/+4
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-7/+7
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-3/+3
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-5/+5
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-10/+10
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-10/+10
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-8/+2
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-9/+9
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-9/+9
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-2/+2
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*	Added various new options to splice command	Clifford Wolf	2014-02-08	1	-5/+105
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*	Now also move net labes to the right position in splice cmd	Clifford Wolf	2014-02-08	1	-3/+10
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*	Added splice command	Clifford Wolf	2014-02-07	1	-0/+252